1. Technical Field
The present invention relates to an AD conversion apparatus. In particular, the present invention relates to an asynchronous successive approximation AD conversion apparatus.
2. Related Art
Asynchronous successive approximation AD conversion apparatuses are known as in, for example, Japanese Patent Application Publication No. 7-170185 (referred to hereinafter as “Patent Document 1”) and Shuo-Wei Mike Chen, Robert W. Brodersen, “A 6b 600MS/s 5.3 mW Asynchronous ADC in 0.13 μm CMOS”, ISSCC 2006 DIGEST OF TECHNICAL PAPERS, Feb. 8, 2006, p.574-575, p.674 (referred to hereinafter as “Non-patent Document 1”). These asynchronous successive approximation AD conversion apparatuses change each bit without synchronizing the changing with a clock.
Asynchronous successive approximation AD conversion apparatuses having a longer processing period for lower bits than for upper bits are known as in, for example, Japanese Patent Application Publication No. 7-264071 (referred to hereinafter as “Patent Document 2”) and Japanese Patent Application Publication No. 2001-292064 (referred to hereinafter as “Patent Document 4”). These AD conversion apparatuses can achieve more accurate comparison results when processing lower bits.
In each successive approximation AD conversion apparatus, the comparator begins the comparison process after the comparison signal output from the DAC settles. However, when the comparator begins the comparison process a long time after the comparison signal output from the DAC settles, the conversion period becomes undesirably long. Accordingly, an asynchronous successive approximation AD conversion apparatus desirably begins comparing the input signal to the comparison signal soon after the comparison signal output from the DAC settles.
Furthermore, since the successive approximation AD conversion apparatuses of Patent Document 2 and Patent Document 3 have longer processing periods for lower bits than for upper bits, the conversion period becomes undesirably long.